`include "C:\Users\lenovo\Desktop\Files\Linear_RISCV\LR_ver_0\src\include\include.vh"
module 	Imm_gen(
    input   	[6:0]			opcode_i,
    input       [31:0]           instr,
    output	reg [31:0]			imm_o
);         wire [2:0]			imm_type_byc;
           wire [5:0]			imm_type_ohc;

    imm_ohc_u ohc_decoder_inst( 
         			opcode_i,
              		imm_type_ohc
            );
    ohc2bin   ohc2bin_inst(
                    imm_type_ohc,
                    imm_type_byc
    );
    
    wire [31:0] imm_I_type,imm_S_type,imm_B_type,imm_J_type_L,imm_J_type_R,imm_U_type;
    imm_all_gen imm_all_gen_inst(
          instr,
          imm_I_type,
          imm_S_type,
          imm_B_type,
          imm_J_type_L,
          imm_J_type_R,
          imm_U_type
);    
    always@(*)begin
        case(imm_type_byc)
             3'b001:imm_o =imm_I_type;
             3'b010:imm_o =imm_S_type;
             3'b011:imm_o =imm_B_type;
             3'b100:imm_o =imm_J_type_L;
             3'b101:imm_o =imm_J_type_R;
             3'b110:imm_o =imm_U_type;
            default:imm_o =32'b0;
        endcase
    end

endmodule





